The present invention relates generally to a memory device, and more particularly to a method of operating a nonvolatile memory device.
Nonvolatile memory devices, which are electrically programmable and erasable with no need for a refresh function of rewriting data at specific intervals, are increasingly in demand.
A NAND flash memory device, one type of nonvolatile memory, uses a page buffer in order to store a large amount of information within a short period of time and to verify whether the program and erase operations have been normally performed. A known page buffer utilizes a single register for temporarily storing data but can also utilize a dual register in order to increase the speed of data program.
The operations performed in a nonvolatile memory device include: a program operation for storing data in a memory cell array; a read operation for reading data stored in a memory cell array; and an erase operation for erasing data stored in a memory cell array.
The program operation is performed through a number of program loops. Each program loop includes a program period and a verification period. The program loop is repeatedly performed within a maximum number of the program loops until all selected memory cells are programmed. If the program operation is treated as a program fail within a maximum number of the program loops, the corresponding memory block treated as a program fail is classified as a bad block. Such classification as the bad block is performed irrespective of the number of fail bits. If the number of fail bits is determined to be within the number of bits correctable by an error correction code (ECC) circuit, the fail bits can be corrected by the ECC circuit when a read operation is performed.
In one technique, fail bits included in the data of programmed memory cells (or a programmed page) are counted and, if the counted number of fail bits is within the number of bits correctable by an ECC circuit, the programmed memory cells are (or the programmed paged is) then treated as a program pass. In this known technique, counting of the fail bits is started at the same point of time irrespective of the type of pages on which a program operation is being performed. For example, some program operation conditions such as the number of program pulses can differ depending on the address of a most significant bit (MSB) page or the address of a least significant bit (LSB) page. In the known technique, however, a constant fail bit count operation is always used irrespective of program operation conditions which vary depending on circumstances. Accordingly, there is a problem in that the program operation is inefficiently performed.